The present invention relates to a PLL (Phase Locked Loop) system for a CRT (Cathode Ray Tube) monitor, which can cope with a deterioration in characteristic due to variations in the loop gain of a PLL.
In general, a PLL system for a CRT monitor uses a PLL loop block designed to frequency-divide an output from a voltage-controlled oscillator (VCO) by using a programmable frequency divider. In the conventional system, since the frequency range of horizontal sync signals input to the PLL loop block is as narrow as about 15 kHz to 80 kHz, no measure has been taken against variations in loop gain due to the programmable 1/N frequency divider.
In recent CRT monitors, however, with an increase in resolution, the frequency range of horizontal sync signals input has extended from about 15 kHz to 150 kHz. For this reason, the loop gain of the PLL loop greatly varies. This worsens unlocked states and jitter in the PLL loop. In practice, to solve this problem, a loop gain is set for the PLL loop so as to prevent the occurrence of an unlocked state in the PLL loop at the expense of jitter characteristics.
FIG. 6 shows a conventional PLL system for a CRT monitor. The conventional PLL system includes a PLL loop block 11 for phase-locking a horizontal sync (H sync) signal 1 which is an input signal, an arithmetic unit 12 for measuring the frequency of the horizontal sync signal 1, and an arithmetic device 13 which operates with a system clock 7 having a predetermined frequency from the PLL loop block 11.
The PLL loop block 11 includes a phase comparator 14 of the edge comparison type, which compares the horizontal sync signal 1 as a reference signal with an FBP signal 4 as a comparison signal and outputs an error signal 2 representing the phase difference, a charge pump 15 for generating a DC voltage in accordance with the error signal 2 from the phase comparator 14, an LPF 16 for converting the DC voltage output from the charge pump 15 into a control voltage, a VCO 17 for changing the oscillation frequency in accordance with the control voltage output from the LPF 16, a programmable 1/N frequency divider 18 in which a frequency division ratio N (N is a positive integer) is variably set in accordance with the frequency of the horizontal sync signal 1, and a CRT drive circuit 19 for performing deflection processing in the CRT on the basis of a horizontal drive (HOUT) signal 3 obtained by frequency-dividing an output from the VCO 17 by using the 1/N frequency divider 18. The CRT drive circuit 19 controls the phase comparator 14 in accordance with the flyback pulse (FBP) signal 4 received through a high-voltage transformer circuit or the like as well as performing deflection processing.
The operation of the conventional PLL system shown in FIG. 6 will be described next with reference to the flow chart of FIG. 7. When the power supply is turned on (step S1), the frequency of the horizontal sync signal 1 is observed (step S2) to check whether the frequency has changed (step S3). If the frequency of the horizontal sync signal 1 has changed, the arithmetic unit 12 calculates a frequency division ratio (step S4) and sets the calculated frequency division ratio in the programmable 1/N frequency divider 18 (step S5). After the frequency division ratio is set, the flow returns to step S2. If it is determined in step S3 that the frequency of the horizontal sync signal 1 has not changed, the flow immediately returns to step S2 to observe the frequency of the horizontal sync signal 1. If the operation of the PLL loop becomes unnecessary, the power supply is turned off to terminate the above operation.
According to the prior art described above, as the frequency range of input horizontal sync signals 1 extends from about 15 kHz to 150 kHz with an increase in resolution, as in recent CRT monitors, variations in loop gain increase, worsening unlocked states and jitter. In practice, a loop gain is so set as to prevent the occurrence of an unlocked state at the expense of jitter characteristics. In addition, as is obvious from equation (2) (to be described later), the loop gain changes with a change in the frequency of the horizontal sync signal 1.
Japanese Patent Laid-Open No. 5-175834 (reference 1) discloses a PLL loop which is made to have an optimal response characteristic in accordance with variations in frequency division ratio and loop gain. In the PLL loop disclosed in this reference 1, since a predetermined switch (selection circuit) is switched in advance, a complicated arrangement is required.
It is an object of the present invention to provide a PLL system for a CRT monitor, which maintains a PLL loop gain constant and prevents the occurrence of an unlocked state and worsening of jitter due to variations in PLL loop gain.
In order to achieve the above object, according to the present invention, there is provided a PLL system comprising phase comparison means for comparing a phase of an input horizontal sync signal with a phase of a comparison signal, variable-capacity charge pump means for outputting a charge pump signal in accordance with a phase error signal output from the phase comparison means, filter means for converting the charge pump signal from the charge pump means into a voltage control signal, a voltage-controlled oscillator for changing an oscillation frequency in accordance with the voltage control signal output from the filter means, frequency division means for performing 1/N frequency division of a frequency signal output from the voltage-controlled oscillator in accordance with a control signal, CRT drive means for performing deflection processing in a CRT on the basis of an output from the frequency division means and outputting, to the phase comparison means, a comparison signal based on a reference signal for a display system which is generated by CRT deflection processing, and arithmetic means for calculating a control signal to be output to the frequency division means from the horizontal sync signal, wherein a charge pump gain of the charge pump means is so controlled as to keep a PLL loop gain constant by compensating for a variation in PLL loop gain due to a change in a frequency division ratio 1/N in the frequency division means.